| abstract |
Inna process sequence for replacing conventional gate electrode structuresnby metal gate structures with large ε, the number of additionalnMasking steps are kept low by, for examplenvery selective etching stepsnbe used, whereby a high degree of compatibility with conventionalnCMOS techniques is maintained. Furthermore, the ones disclosed hereinnMethod, compatibilitynon techniques in the transistor area and in metallization areasnmaintaining the integration well-established deformation-inducingnMechanisms at the transistor level and at the contact level is possible. |