http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102006001997-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0207 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 |
| filingDate | 2006-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b789caf3a2128a10008dcfd870f8b814 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9147ff4a8e53d9d2dd0e9555c9a56afc |
| publicationDate | 2007-11-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102006001997-B4 |
| titleOfInvention | Semiconductor circuitry |
| abstract | The invention relates to a semiconductor circuit arrangement with at least one first and second field effect transistor (T1, T2), the field effect transistors each having at least two active areas (AA11 to AA22) each with a source area, a drain area and a channel area lying in between, the surface of the Channel regions insulated by a gate dielectric, a gate (G11 to G22) for driving the channel regions is formed. At least one active area (AA22) of the second field effect transistor (T2) is arranged between the at least two active areas (AA11, AA12) of the first field effect transistor (T1), which results in a reduced mismatch between the two transistors due to temperature and local spacing. |
| priorityDate | 2006-01-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 18.