http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102005056493-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2211-5642 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-26 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5628 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-5642 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-34 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-24 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-34 |
| filingDate | 2005-11-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_40f45dcb35a3a431d4a0d306d9533dd1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7289517e3b9919f6c3d41462b0e8fe9a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7fca471c24f26b9fcdb217fb15a72424 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_da6ee17c5af9f06daa37cd071e75b89e |
| publicationDate | 2006-08-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102005056493-A1 |
| titleOfInvention | Multi-bit nonvolatile semiconductor memory device and method of operation |
| abstract | The invention relates to a multi-bit nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device, and a method of operating a multi-bit nonvolatile semiconductor memory device. The multi-bit nonvolatile semiconductor memory device comprises a sub-buffer circuit which stores a logical value as sub-buffer data and selectively tilts the logical value of the sub-buffer data in accordance with a sub-buffer signal according to the bit line voltage level, the memory device in a read mode reading the threshold voltage states of the nonvolatile memory cells. and operable in a programming mode that programs the threshold voltage states of the nonvolatile memory cells, the page buffer circuit selectively inhibiting the logic value of the main latch data by the bit line in the programming mode in response to the sub-latch data. Use in storage technology. |
| priorityDate | 2004-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.