http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-102005006343-A1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36f8253f3d0d59bcd9259217d4385d10 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-225 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076 |
| filingDate | 2005-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9dffb15b60afbc46c14dbbceec73456 |
| publicationDate | 2006-08-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-102005006343-A1 |
| titleOfInvention | Integrated semiconductor memory with isochronous access control |
| abstract | Onenintegrated semiconductor memory comprises a first input amplifier (21),noppositena second input amplifiern(22) lower sensitivity to level fluctuationsnhas its respective input signal. A control circuitn(26) controls a controllable switch (28) such that whennApplying a noisy clock signal to the integrated semiconductor memorynthe less sensitive input amplifier (23) for generating aninternal clock signal (Cint1) is used. If, however, a low-noise clock signalnis applied to the integrated semiconductor memory controls thenControl circuit (26) the controllable switch (28) such thatnfor generating the internal clock signal (Cint2) the more sensitive input amplifier (22)nis verwednet. The switching of the controllable switch (28) takes placenafter evaluation of a bit sequence which is sent to a further input connection (E23)nof the integrated semiconductor memory is applied. |
| priorityDate | 2005-02-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 35.