http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10107427-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d231147f38595bbe3114b758cba4a298 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C29-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-44 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C8-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F12-08 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C29-00 |
| filingDate | 2001-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2007-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9254236785e03a6d452bb874cc5dc88 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f6218f723c2e9844db15d7a201053d22 |
| publicationDate | 2007-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-10107427-B4 |
| titleOfInvention | Semiconductor memory device |
| abstract | A semiconductor memory device, comprising: a main memory (101) having at least one redundant main memory memory cell array (DMAR), a sub-memory (102) having at least one redundant sub-memory memory cell array (SMAR), a plurality of data transfer bus lines (TBL) between the main memory (101) and the sub-memory (102), which are configured so that data can be transferred bidirectionally, redundant transfer bus data lines (TBLR) between the redundant main memory memory cell array and the redundant sub memory memory cell array, which are configured so that data can be transmitted bidirectionally, a redundancy circuit for defect removal for defects that are in the main memory, with at least one address replacement determination element (2001, 2002), which determines from the address determined by an external component during a read or write, the sub memory address of a redundant memory cell (SMCR) of the redundant sub memory memory cell array (SMAR) to be replaced is accessed from the external component, the at least one address replacement determining element (2001, 2002) being formed, a sub memory column selecting signal (SYm), a bank selecting signal (BS) selecting a particular bank in the main memory (101), and a main memory line selecting signal (DXn), ... |
| priorityDate | 2000-02-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 51.