http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10107125-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c16d2144a81bfa32a665dca1e93c3d37 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-0002 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B99-00 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76897 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-522 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8239 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate | 2001-02-15-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2004-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d714146bf7ccb2fd456ede989ab42d27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0aa31c6ec11def5f3b9f4bcd33ffa1ef |
| publicationDate | 2004-02-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-10107125-B4 |
| titleOfInvention | Method of forming contact holes in an integrated circuit device by selectively etching an insulation layer in order to enlarge the self-aligning contact area adjacent to a semiconductor region, and contact thus formed in an integrated circuit device |
| abstract | Contact in an integrated circuit device with a substrate (51) and - With a plurality of connecting lines (62a, 62b) consisting of a gate insulation layer (55) on the substrate (51), a line layer (57, 57a) and a top insulation (59, 59a); and With semiconductor regions (65, 65a, 65b) in the substrate (51) between the connecting lines (62a), - With an etch stop layer (67) at least on the side walls of the connecting lines (62a, 62b) and on the substrate (51); and - With an interlayer insulation (79, 85, 87) and with electrical contacts (83a, 83b) through the interlayer insulation (79, 85, 87) to the semiconductor regions (65, 65a, 65b); and - With further insulation layers (69a ', 69b', 71a, 71b) on the etching stop layer (67) on the connecting lines (62a, 62b) characterized in that the further insulation layers (69a ', 69b', 71a, 71b) adjoining the etching stop layer (67) on the connecting lines (62a, 62b) are formed in a lower region towards the substrate from a first material and in the upper region from a second material , wherein the second material has a greater layer thickness than the first material and the second material forms an overhanging side wall insulation (71a, 71b). |
| priorityDate | 2000-03-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.