http://rdf.ncbi.nlm.nih.gov/pubchem/patent/DE-10008683-B4
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d7576285d411d00c697e07270d2814a |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823475 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-28512 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76877 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76802 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-28 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8244 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-285 |
| filingDate | 2000-02-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2006-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4d039bc14ceecd0c19d72edc8a9e8a4e http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_fd83370844489734498ebe92a8adaf4a |
| publicationDate | 2006-01-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | DE-10008683-B4 |
| titleOfInvention | Semiconductor device and related manufacturing method |
| abstract | Semiconductor device with a semiconductor substrate (1), a pair of low-concentration impurity regions (3a, 3b, 3c, 3d) having a relatively low impurity concentration and separated from each other by a gap formed on a surface of the semiconductor substrate (1), a gate electrode (7a, 7b) disposed between the pair of low-concentration impurity regions (3a, 3b, 3c, 3d) and on the semiconductor substrate (1) with a gate insulating film (6a, 6b) interposed therebetween; 8a, 8b) covering the gate electrode (7a, 7b), an interlayer insulating film (10, 110, 210) covering the gate electrode (7a, 7b) and the protective film (8a, 8b) having a hole (11a to 11d, 111a to 111d, 211a to 211d), each of which Reaches low concentration impurity regions (3a to 3d) and has an etch rate which is greater than an etch rate of the protective layer (8a, 8b) when a prescribed etchant is used, a high-concentration impurity region (4a-4d) having a relatively high impurity concentration within each of the low-concentration impurity regions (3a-3d) ... |
| priorityDate | 1999-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 31.