http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CS-222951-B1
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d2b70d85fa251203924342bc4a4e8e84 |
| classificationIPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C15-00 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-00 |
| filingDate | 1979-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8816c290c4ff09d336a496223d7b45eb |
| publicationDate | 1983-08-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CS-222951-B1 |
| titleOfInvention | Associative storage device |
| abstract | The invention is within the field of computer technology, and more particularly, the search memorynwith integrated microcircuits panand is designed to improve performancenwhile performing arithmetic operations. younThe target is achieved by blocking the address memory module blocksngiven in the shape of a rectangular matrix and containnfour modules with order logsnthe buses are connected to mode addersntwo, wherein the addition and subtraction operations are effected by summing the signals in ynof the respective field busesnmodules of this block and block of the previous onenrow matrix, switched two-channelnthe switches that are connected to the inputnpy adder modulo two second pair mondulů of this block. For performing operationsnmultiplication and division, one pair of memory modes is introduced into each blocknsecond and third two-channel switchesnand such elements of a logical product. |
| priorityDate | 1979-01-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 21.