http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-212086173-U

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e7d3267351fe66e96455bf50cc0c65eb
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03L7-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06Q20-38
filingDate 2020-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_52e3f11aeb5d490f7b2786f710965b8f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7e91792147eb5ba6a9d4b2065d2ea55d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5636cec9c8e9c88d5a70b041851fc66c
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http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_590203201235cc046bb852b0db05a283
publicationDate 2020-12-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-212086173-U
titleOfInvention Clock circuit, computing chip, computing board and digital currency mining machine
abstract The present disclosure relates to a clock circuit, a computing chip, a force plate and a digital currency miner. The clock circuit comprises M stages of clock driving circuits which are connected in series, M is an integer not less than 2, and N inverters which are connected in series are arranged between the input end and the output end of each stage of clock driving circuit in the M stages of clock driving circuits, wherein N is an odd number not less than 3. The clock circuit can provide a clock signal with good performance.
priorityDate 2020-06-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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