http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-211238253-U
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_e3c45b3de946d2b915efdbc227ab7859 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_a62555ff12316a9a118542896b4c0af7 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G02F1-1362 |
| filingDate | 2019-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf3790d9952ff59b221a5f41598bfda2 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_910f1f970bbee7193f3a57424a5e48c3 |
| publicationDate | 2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-211238253-U |
| titleOfInvention | Array substrate, display panel and display device |
| abstract | The embodiment of the utility model provides an array substrate, display panel and display device, including the substrate; the gate electrode layer, the gate insulating layer, the drain-source metal layer and the passivation layer are stacked on the substrate, wherein the gate electrode layer is arranged close to the substrate; a plurality of clock signal lines are arranged on the gate electrode layer; a plurality of gate array driving connecting lines are arranged on the drain-source metal layer; a plurality of first via holes penetrating through the gate electrode layer and a plurality of second via holes penetrating through the drain-source metal layer are formed in the passivation layer; the passivation layer, the first via hole and the second via hole are all provided with a conductive film layer; each clock signal line is correspondingly coupled with the corresponding gate array driving connecting line one by one through the conductive film layer; the gate array driving connecting lines are provided with projections on the plurality of clock signal lines, and the projection areas of the gate array driving connecting lines on the plurality of clock signal lines are the same. The embodiment of the utility model provides a can make the electric capacity between each clock signal line and the array connection line the same, it is bad to avoid GOA to produce the striae. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114002885-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114002885-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023137797-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2022088079-A1 http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115210802-A |
| priorityDate | 2019-12-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 47.