http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-210402070-U
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4748427a34a9a22f211f73c58599fe18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G05B19-042 |
| filingDate | 2019-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2020-04-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d7330b42794674735705e8048930ae5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b470a1ca97d79e044bbc582131b5c994 |
| publicationDate | 2020-04-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-210402070-U |
| titleOfInvention | Dual-DSP digital signal processing board card based on CPCI |
| abstract | The utility model provides a two DSP digital signal processing integrated circuit boards based on CPCI, including 2 DSP chips, 2 FPGA chips, 12 SDRAM chips, 2 Flash chips, PCI-PCIE bridge chip, CPCI connector, FMC HPC connector, MAX3160 chip, AD5668 chip, the CPCI connector includes J1 interface, J3 interface, J4 interface, J5 interface, 2 DSP chips are DSP1, DSP2 respectively, connect the communication through Hyperlink and 1X's SGMII between 2 DSP chips, 2 FPGA chips are FPGA1, FPGA2 respectively, every DSP is connected with FPGA1 through a 4X's SRIO interface respectively, 4 SDRAM chips are connected respectively to every DSP, 1 Flash chip is connected respectively to every DSP. Through the utility model discloses, with the DSP digital signal processing integrated circuit board signal processing ability and the data cache performance that solve prior art existence low, the poor problem of expansibility. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114281737-A |
| priorityDate | 2019-09-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.