http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-210109806-U

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_95d504eaa4db2a30d6e0578181afe15e
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F15-16
filingDate 2019-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
grantDate 2020-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e48d594e044ad1828b9d27463d8620ba
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5c38117f5981dfd001755b7cf7af7aa4
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5da10197fcab3170a1cf985c9961cfd2
publicationDate 2020-02-21-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-210109806-U
titleOfInvention GPU interconnection structure
abstract The utility model provides a GPU interconnection structure, including the first module shell and the second module shell of superpose, be equipped with first GPU integrated circuit board in the first module shell, be equipped with second GPU integrated circuit board in the second module shell, first GPU integrated circuit board and second GPU integrated circuit board are connected through high-speed connector, are connected with the apron on the second module shell. The utility model discloses an ingenious design to GPU interconnection structure makes its integrated circuit board width that has solved many GPU interconnections too big, can't erect the problem of inserting under limited quick-witted case high condition.
priorityDate 2019-06-29-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 19.