http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-208904014-U
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_90da52f31c0d9b43d76c6d6cd90f56c2 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-73265 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48091 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32225 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-92247 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-32145 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-48227 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-065 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488 |
| filingDate | 2018-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2019-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5e377ac8f879ccc9a3b29fa2d5307917 |
| publicationDate | 2019-05-24-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-208904014-U |
| titleOfInvention | A multi-chip stacked fan-out package structure |
| abstract | The utility model discloses a multi-chip stacked fan-out packaging structure, comprising: a first dielectric layer; a first metal column, wherein the first metal column is arranged in the first dielectric layer and penetrates the upper and lower surfaces of the first dielectric layer; Two metal pillars, the second metal pillar is arranged in the first dielectric layer and penetrates the upper and lower surfaces of the first dielectric layer; the first chip, the first chip is embedded in the first dielectric layer and penetrates the upper and lower surfaces of the first dielectric layer; Two chips, the second chip is arranged on the back of the first chip; leads, the leads electrically connect the pads of the second chip to the first metal pillars; the second dielectric layer, the second dielectric layer covers the second chip, the leads and the first metal pillars surface; the third chip, the third chip is flip-chip bonded to the second metal pillar; the third dielectric layer, the third dielectric layer is located on the bottom surface of the first dielectric layer; the metal interconnection layer, the metal interconnection layer is electrically connected to the first metal pillar , a second metal pillar and a pad of the first chip; a fourth dielectric layer, the fourth dielectric layer is located on the bottom surface of the third dielectric layer; and an external solder ball, which is electrically connected to the metal interconnection layer. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111128903-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115050654-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-111128903-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115050654-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114975333-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113192854-A |
| priorityDate | 2018-11-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 30.