http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-207265048-U
Outgoing Links
Predicate | Object |
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assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c944260a6bc6150a22899f94ff0af27b |
classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-64 |
filingDate | 2017-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
grantDate | 2018-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_224f22dadc6a7a60b56c396cb0d04996 |
publicationDate | 2018-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
publicationNumber | CN-207265048-U |
titleOfInvention | Semiconductor memory |
abstract | The utility model provides a kind of semiconductor memory,Including substrate and the multiple capacitors being arranged in substrate,The capacitor includes lower electrode layer,Dielectric layer and upper electrode layer,Wherein,The dielectric layer and the upper electrode layer are sequentially formed at the surfaces externally and internally of the lower electrode layer,The outer surface of the lower electrode layer has the combination shape of capacitance pattern hole and capacitance profiled orifice,The lower electrode layer has the Part I close to the substrate and the Part II away from the substrate,The Part II corresponds to the capacitance pattern hole and has the first gradient,The Part I corresponds to the capacitance profiled orifice and has the second gradient,Second gradient is less than first gradient,Capacitor profile in the semiconductor memory is more vertically changed,It thus avoid the generation of short circuit phenomenon between capacitor,Improve the performance of finally formed semiconductor memory. |
isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-107689362-A |
priorityDate | 2017-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.