http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-206208930-U
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5d30d9d6a51dae78bf52af1397d9a666 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R1-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G01R31-26 |
| filingDate | 2016-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2017-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc4397ec3aecc46811c48cd393c74bfe http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d4439a2454d5edb44fb4c7d43aaf818c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3c9c7418cc1b5cc822c353d4c33a8c58 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54a3deea954b6bc71cd2f1d7f4d11030 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d7a85ecbe3f822321c0531fdb0e9c90c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_0a13b954a33bf32489c5949ba49bafa3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e0eb63583de7d7f485f18bbbc443bad1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c42a1ee049c7479814918b2e53342851 |
| publicationDate | 2017-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-206208930-U |
| titleOfInvention | A kind of autoregistration power semiconductor chip test fixture |
| abstract | Title of the present utility model is a kind of autoregistration power semiconductor chip test fixture.Belong to power semiconductor technical field of measurement and test.It is mainly and solves the problems, such as that existing test operating procedure is cumbersome, efficiency is low, easily causes test data of chip deviation and chip outward appearance is scratched and damaged.It is mainly characterized by：Upper fixture is made up of minus plate, retaining spring, fairlead, negative electrode briquetting, negative electrode sampling probe and center gate pole sampling probe；Retaining spring, the upper end of negative electrode briquetting are fixed on minus plate, and lower end is located in fairlead and is fixedly connected with fairlead；Negative electrode sampling probe and center gate pole sampling probe are arranged on negative electrode briquetting；The lower clamp is constituted by holding piece disk and anode sampling probe；It is described to hold chip positioning groove, the positioning boss that cooperation is provided between piece disk and fairlead.There is the utility model chip to be directed at the characteristics of changing convenience, small parasitic pressure drop, simple test operation and service efficiency high, be mainly used in power semiconductor chips test. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-110389240-A |
| priorityDate | 2016-11-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.