http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-203013269-U
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d6e2135bb387f709e0f1cc00a6345ff8 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-10 |
| filingDate | 2012-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2013-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4150da1f0ddceb832324fa02774bc245 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_916557e1bf89bc436b6f3db2fda9a53a http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33806476fa8d33dd4c4602c21873650b |
| publicationDate | 2013-06-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-203013269-U |
| titleOfInvention | Circuit for acquiring DDR2 (double data rate 2) data of 500 Mb/s by virtue of FPGA (field programmable gate array) |
| abstract | The utility model discloses a circuit for acquiring DDR2 (double data rate 2) data of 500 Mb/s by virtue of an FPGA (field programmable gate array). The circuit comprises an analogue/digital conversion chip which outputs DDR2 data having the maximum rate of 500 Mb/s and an FPGA module, wherein the FPGA module comprises a DCM (direct-current main) module, a key processing module, a storage module and an IDDR (intelligent digital disk recorder) module. The circuit further comprises a display screen, a first key for adding 1 to the phase of the DCM module in case of being pressed, and a second key for subtracting 1 to the phase of the DCM module in case of being pressed. The circuit disclosed by the utility model is used for synchronizing a clock of the analogue/digital conversion chip by virtue of the DCM module in the FPGA, achieving a phase adjustment on the output data via the keys, and displaying the output data of the analogue/digital conversion chip on the display screen, the phase of the DCM module can be adjusted via the keys in the case that difference exists between the output data and actual data, so that the finally output data is the data of the analogue/digital conversion chip, and then normal acquisition for the DDR2 data of the analogue/digital conversion chip is achieved via a manual mode, thus saving cost. |
| priorityDate | 2012-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 48.