| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_75f2b416cfb00bc36e84b742cac35d4d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-171
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16225
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-81
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-181
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-18161
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-1712 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-17
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-481
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-81 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-48
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-56
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-50 |
| filingDate |
2022-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bd0dc875ad2e64889ae5a084896b4210
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_33a21d0235f20bd5b1740004157c1f3d
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b2f144b017481a56b390272dd4a79c76
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_6b23baad17ac8c64273d51af1b5b4388 |
| publicationDate |
2022-10-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-115241075-A |
| titleOfInvention |
Semiconductor packaging structure and preparation method based on TSV interconnection |
| abstract |
The present invention provides a semiconductor packaging structure and preparation method based on TSV interconnection. One end of a TSV column is directly used as a connecting piece, which can reduce the preparation process of a metal connecting piece, thereby saving costs and reducing interconnection impedance. The packaging process of the TSV interposer; the second dielectric layer with the trench can be used as the exposed TSV pillar to protect the sidewall to improve the packaging stability; when the surface of the TSV pillar has an insulating layer, the first dielectric layer covering the TSV pillar is formed. Metal seed layers at both ends or etching to remove insulating layers can also improve metal interconnectivity. |
| priorityDate |
2022-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |