http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115172168-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_079d992c41097c13960c9a57cb55f608 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_238d2a330d6131be1b82568628dffd28 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 |
| filingDate | 2022-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1a01246efdb90313c1afe3c4c16733a3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2fa8b204a3b48fba6de0b7e65fe9b56c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_56412dc342ff5eb20c19f2bebfc0cc29 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_d9c2458c1b5fb4d6aae038db1fa8b6ec |
| publicationDate | 2022-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-115172168-A |
| titleOfInvention | A preparation method of multi-threshold stacked nanosheet GAA-FET device array |
| abstract | The invention relates to a method for preparing a multi-threshold stacked nano-sheet GAA-FET device array, wherein the formation process of a high-k dielectric layer in a device wrap-around gate is as follows: first, the interface is oxidized, and then a non-polar high-k dielectric layer is deposited and covered, Then deposit and cover the first type of polar high-k dielectric layer, anneal, and then remove it in part of the device array through an etching process, so as to subsequently form the first type of device thresholds; re-deposit and cover the second type of polarity high-k dielectric, carry out Annealing, and then removing in part of the device array through an etching process to form a second type of device threshold, and thereby obtaining more device thresholds by combining different coverage areas. The present invention changes the Si-O polarity intensity in the interface oxide layer by covering the high-k dielectric layers of different polarities in the integrated manufacturing of the GAA-FET device array, thereby realizing the manufacturing method of different device thresholds. |
| priorityDate | 2022-07-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID415749369 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID72157 |
Total number of triples: 20.