http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115172159-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_bca3f1e125e663ace01743e658f98c32 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02348 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02164 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02126 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-0214 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02145 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02271 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-4757 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-3105 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-318 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-316 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-473 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-471 |
| filingDate | 2022-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ed0d42cc3e3b95f0b7b3417f4530dec8 |
| publicationDate | 2022-10-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-115172159-A |
| titleOfInvention | Stress balancing method for semiconductor wafer and its application |
| abstract | The invention provides a stress balancing method for a semiconductor wafer and an application thereof, and relates to the technical field of semiconductors. The stress balancing method of the invention comprises: growing a film layer on the backside of the semiconductor wafer in a warped state, and then curing it by ultraviolet rays to increase the Increase and control the stress of the film layer to adjust the warpage state of the semiconductor wafer. The invention solves the technical problem that the balance layer or the stress buffer layer in the prior art is not effective in balancing the front-side stress of the wafer, achieves an effective balance of the front-side stress of the wafer, avoids defects in process and reliability caused by the front-side stress, and avoids the The technical effect of severe warpage of semiconductor wafers. |
| priorityDate | 2022-08-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.