http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115102528-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4a7426bd88e3c9f474ac5e2e5f065e6d |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03K5-2481 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03K5-24 |
| filingDate | 2022-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9a2cdf0b985cafe2d75ec2d8846a30f1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c1461502d288f23e66782ac00e564b58 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4061f3f029f8b901c981c2fbcf949eb9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2f8836aff09c61aad50354ca1ca0976b http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_298cfe2d59e5030effc5f7c31b4da847 |
| publicationDate | 2022-09-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-115102528-A |
| titleOfInvention | An ultra-low-power high-speed dual positive feedback comparator circuit |
| abstract | The invention belongs to the field of analog-to-digital conversion integrated circuits, and in particular relates to an ultra-low power consumption and high-speed dual positive feedback comparator circuit, comprising a dual positive feedback comparison circuit, which is provided with a first multiple common source stage positive feedback circuit and a second multiple Latch positive feedback circuit ; Self-reset clock circuit. Through the double voltage positive feedback circuit, the first positive feedback adopts a symmetrical common source circuit, and the drain outputs are respectively connected to the gates of the complementary circuits of the symmetrical circuits, and the symmetrical circuits form positive feedback with each other; the second positive feedback uses Latch latching Structure, through the back-to-back inverter structure, the output of the first positive feedback is used as the input, and the signals with slight differences can be accurately and quickly compared. Using self-reset clock control during sampling, the comparator clock is low level. After sampling is completed, the comparator clock automatically becomes high level, and the comparator starts to work. Since there is no static current that is directly connected to the ground during operation, it can reach extremely low levels. power consumption. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116545422-B http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116545422-A |
| priorityDate | 2022-06-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 |
Total number of triples: 20.