| abstract |
Disclosed herein are methods for fabricating IC structures that include stacked vias that provide electrical connections between metal lines of different layers of a metallization stack, and the resulting IC structures. An example IC structure includes a first metallization layer and a second metallization layer, which include a bottom metal line and a top metal line, respectively. The IC structure also includes a via having a bottom via portion and a top via portion, where the top via portion is stacked over the bottom via portion (thus, the via may be referred to as a "stacked via"). The bottom via portion is coupled to and self-aligned with the bottom conductive line, and the top via portion is coupled to and self-aligned with the top conductive line. The bottom via portion is formed using subtractive patterning, while the top via portion can be formed using a different fabrication technique, such as damascene fabrication. |