| abstract |
Described herein is a fabrication process and resulting transistor device having trench contacts having two parts stacked on top of each other (first trench contact (TCN1) and second trench contact (TCN2)). In this transistor device, TCN1 can be self-aligned with adjacent gates and can be used to make cell-level connections, and TCN2 can also make cell-level connections and can be provided after the formation of self-aligned TCN1, and has an inverted taper shape, the spacers around the TCN2 can be a higher dielectric constant dielectric material than conventional spacer materials, and the VCG can be formed without any gate capping layer present or after using only a thin temporary gate capping layer . The fabrication processes and transistor arrangements described herein may provide several improvements in increased edge placement error tolerance, cost efficiency, and device performance. |