http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114883266-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_386edcf52001ff8bc7805d863b0f0d95 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-7816 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66681 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823481 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088 |
| filingDate | 2022-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c97527a6304eefaa632144630449ad79 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_cac99f586d0b9c5cd37437a2abb5a8f4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_8a8ff079cca6fee04e7509b480e9bba6 |
| publicationDate | 2022-08-09-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-114883266-A |
| titleOfInvention | LDMOS device and preparation method thereof |
| abstract | The invention provides an LDMOS device and a preparation method thereof. The method includes the steps: S1: providing a semiconductor substrate, forming a first shallow trench and a second shallow trench; S2: forming an isolation structure, a gate structure and a P-type body region filled in the first shallow trench; S3 : forming sidewall spacers; S4: performing ion implantation to form an N-type source region and a P-type source region; S5: forming a conductive material layer on the surface of the N-type source region, P-type source region and gate structure to obtain a pretreatment structure ; S6: forming an interlayer dielectric layer covering the pretreatment structure, forming a number of contact holes in the interlayer dielectric layer, respectively electrically connected to the N-type source region, the P-type source region and the conductive material layer on the surface of the gate structure. By adopting the present invention, most of the process steps required for forming the P-type body region trenches alone can be omitted, the complexity of the process is reduced, the alignment difficulty is greatly reduced, and the device characteristic shift caused by inaccurate alignment can be significantly reduced. It is possible to reduce the use of photomasks and reduce production costs. |
| priorityDate | 2022-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 24.