| abstract |
The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage trimming. For example, memory cells may include gate electrodes, ferroelectric structures, and semiconductor structures. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes are laterally separated and individually on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure. |