| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5380a863d0c023dc7c9e2ae04b44b6a1 |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16145
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-16135
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11462
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-119 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-94
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3107
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-81 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 |
| filingDate |
2021-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_829efe76306624966644bbbc11b4cdf9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_173a2e03959ccf2a478b1618c4706bd8
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_364111b1b2a1ff8b8cd88a5809c4d5ec |
| publicationDate |
2022-07-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-114823357-A |
| titleOfInvention |
Wafer-level packaging method and packaging structure |
| abstract |
The present invention provides a wafer-level packaging method and a packaging structure. The wafer-level packaging method includes: providing a first wafer, a plurality of first chips are formed in the first wafer, and a surface of the first chip has a first chip. a bonding pad, a first dielectric layer exposing the first bonding pad is formed on the surface of the first wafer; a plurality of second chips are provided, the surface of the second chip has a second bonding pad, and a second bonding pad exposed on the second chip is formed The second dielectric layer of the pad; the second dielectric layer is arranged opposite to the first dielectric layer, so that the second chip is bonded to the first wafer, and the position of the second chip and the first chip corresponds to that of the first pad. A first void is formed between the first pad and the second pad; a first conductive bump for electrically connecting the first pad and the second pad is formed in the first void; and a package layer covering the second chip is formed. The present invention simplifies the packaging process. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115172192-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115332169-A |
| priorityDate |
2021-01-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |