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filingDate 2020-08-11-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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publicationDate 2022-07-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-114762107-A
titleOfInvention Jump-level vias in metallization layers for integrated circuit devices
abstract An integrated circuit device can be formed that includes an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes: a first level, the first level includes a first dielectric material layer; on the first level the second level, wherein the second level includes a second layer of dielectric material; a third level above the second level, wherein the third level includes a third layer of dielectric material; at least one power/ground structure, at the second level and at least one skip-level via at least partially through the first level of the first dielectric material layer, through the second level of the second dielectric material layer and at least partially through the third level of the third dielectric material The layer extends, wherein the at least one jump-level via includes a continuous conductive material.
priorityDate 2019-12-26-04:00^^<http://www.w3.org/2001/XMLSchema#date>
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