http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114628487-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f7cbf6a1a55b84ca15e7f7de42102989 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_35c057a2d73ae88b28d28f9bb2a08715 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0603 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336 |
| filingDate | 2020-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_22bc739931693e9895263405b27e39a7 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c475787d6b62daf7fbb0a65d9679e9d9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_68d82f6a37b26f60e0e505e037c5f791 |
| publicationDate | 2022-06-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-114628487-A |
| titleOfInvention | Semiconductor structure and method of forming the same |
| abstract | A semiconductor structure and a method for forming the same, the forming method includes: providing a substrate, including a device region and an isolation region between adjacent device regions, a fin is formed on the substrate of the device region, and a fin is also formed on the substrate of the device region There is a dummy gate layer across the fin, the dummy gate layer covers part of the top and part of the sidewall of the fin, the base of the isolation region and the dummy gate layer on both sides of the isolation region form a trench; formed on the sidewall of the trench stress buffer layer; after the stress buffer layer is formed, a dielectric isolation structure is formed in the trench; after the dielectric isolation structure is formed, the dummy gate layer is removed. The stress buffer layer blocks the path for the high stress generated by the dielectric isolation structure to be released into the dummy gate layer, thereby reducing the probability of generating grain boundaries in the dummy gate layer due to the stress release path, and at the same time, reducing the dielectric isolation. The probability that the layer is diffused into the dummy gate layer due to deformation and forms a protrusion is beneficial to the subsequent removal of the dummy gate layer, thereby improving the performance of the semiconductor structure. |
| priorityDate | 2020-12-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.