| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_355555c24076b659de494363997bd57d |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-229
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C2207-2281 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1066
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4074
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-109
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1045
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-419
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-417
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1069 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C7-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4076
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-417 |
| filingDate |
2021-11-29-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_1d022e6ecf47f53c2fdb5f23d984d4ab |
| publicationDate |
2022-06-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-114582388-A |
| titleOfInvention |
Timing and related apparatus, systems, and methods for disturbed-reduced read and write operations |
| abstract |
The present application relates to timing and related apparatus, systems and methods for read and write operations with reduced interference. An apparatus may include a first DQ pin, a second DQ pin, and an output circuit. The output circuit may be configured to provide a first signal at the first DQ pin and a second signal at the second DQ pin based on a timing pattern. In some embodiments, based on the timing pattern, the output circuit may be configured to delay the first signal relative to the second signal such that rising and falling edges of the first signal do not coincide with the second signal The rising and falling edges of the signal coincide. In these or other embodiments, the device may further include a mode register, wherein the slew rate of the first signal is based at least in part on a value of the mode register. Associated systems and methods are also disclosed. |
| priorityDate |
2020-12-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |