http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114566465-A

Outgoing Links

Predicate Object
assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_0aa0074f365b254e7c579c5ab713e920
classificationCPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0847
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823418
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0266
classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-08
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8234
filingDate 2022-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3e8492cae99eba4bf0336df75fa39db7
publicationDate 2022-05-31-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-114566465-A
titleOfInvention MOS device for electrostatic discharge protection and preparation method thereof
abstract The present invention provides a MOS device for electrostatic discharge protection and a manufacturing method thereof, wherein the method includes: forming a first lightly doped drain region in the low-voltage device region by using a first mask, wherein, in the first A first window is formed between the lightly doped drain regions; a second lightly doped drain region is formed in the high voltage device region and the low voltage device region by using a second mask. The present application uses the first mask to form a patterned first lightly doped drain region, then forms a second lightly doped drain region in the first window, and finally forms a patterned first lightly doped drain region and a second lightly doped drain region in the first window. The first drain terminal is formed on the drain region, so that the ESD ion implantation region at the bottom of the first drain terminal can be directly formed while the first lightly doped drain region and the second lightly doped drain region are formed, so that the first drain terminal is not additionally added. In addition to the ESD ion implantation process at the bottom of the drain terminal, the manufacturing cost of the MOS device is saved, the trigger voltage of the device is also reduced, and the robustness of the device is improved.
priorityDate 2022-02-28-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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isDiscussedBy http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID419578708

Total number of triples: 18.