http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114361028-A

Outgoing Links

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assignee http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_d548802412bee686a2ff1f8223d916dd
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classificationIPCInventive http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-06
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-50
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-329
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-861
filingDate 2021-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_401c30e3b8147f57b6110e92e92f99c1
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_54219a174719d83e5be26f443f9dfb15
publicationDate 2022-04-15-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-114361028-A
titleOfInvention A chip and method of making the same
abstract The present application discloses a chip and a manufacturing method thereof. The manufacturing method of the chip includes: polishing one side of a high-purity monocrystalline silicon wafer, and polishing one side of a low-purity monocrystalline silicon wafer; Align the polished surface of the high-purity single crystal silicon wafer with the polished surface of the low-purity single crystal silicon wafer for pre-bonding to form a pre-bonded silicon wafer, and place the pre-bonded silicon wafer on the bonding inside the chamber to form a bonded silicon wafer; polishing the high-purity single-crystal silicon wafer surface of the bonded silicon wafer, and sequentially forming an epitaxial layer and a functional device. The present application uses a low-purity single-crystal silicon wafer as a sacrificial layer, thereby reducing the thickness of the entire high-purity single-crystal silicon wafer and greatly reducing the material cost of the high-purity single-crystal silicon wafer and chips.
priorityDate 2021-03-18-04:00^^<http://www.w3.org/2001/XMLSchema#date>
type http://data.epo.org/linked-data/def/patent/Publication

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Total number of triples: 31.