http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114334970-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_4e0669770daabd8a1c731d201ad685de |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-8242 |
| filingDate | 2020-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f2aad1f08039b7a7017f73b134852479 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_23576b1b7aceea5ca136135c62cb8e2d |
| publicationDate | 2022-04-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-114334970-A |
| titleOfInvention | Semiconductor structure and preparation method thereof |
| abstract | The invention relates to a semiconductor structure, comprising: a substrate; the first dielectric layer is positioned on the upper surface of the substrate; the capacitor penetrates through the first dielectric layer along the thickness direction of the first dielectric layer, extends to the upper surface of the first dielectric layer and is electrically connected with the drain electrode of the selective switch transistor; the second dielectric layer is positioned on the upper surface of the first dielectric layer; the first metal layer is positioned on the upper surface of the second dielectric layer; the first conductive plug is positioned on the upper surface of the conductive metal layer and is electrically connected with the conductive metal layer; the third dielectric layer is positioned on the upper surface of the second dielectric layer; and the second metal layer comprises a bit line, is positioned on the upper surface of the third dielectric layer and is electrically connected with the plate line metal layer. The capacitor area is separated from the limitation of the area of a semiconductor device, the capacitor with enough size can be kept under the condition of unit shrinkage, and the storage performance of the unit is greatly improved. |
| priorityDate | 2020-09-30-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.