| abstract |
The invention discloses a depletion-mode SiC heterojunction transistor epitaxial structure and a preparation method thereof. The depletion-mode SiC heterojunction transistor epitaxial structure sequentially includes from bottom to top: a SiC substrate layer, an N-type highly doped 4H- SiC buffer layer, N-type drift layer with superjunction structure, 4H‑SiC channel layer, 3C‑SiC barrier layer; the epitaxial structure has high electron mobility, and can reduce the leakage channel and avoid the growth area of the substrate facet The leakage current is large and causes the device to fail. |