http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114220662-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_fc5a3ebaf351bfeedd60dfc8752c5f34 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B23K37-0443 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01G9-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01G9-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01G9-15 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01G9-045 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01G9-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B23K37-04 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01G9-15 |
| filingDate | 2021-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9fbec08ceb4b69af112bfe54f687ffce |
| publicationDate | 2022-03-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-114220662-A |
| titleOfInvention | Laminated solid aluminum electrolytic capacitor with low ESR (equivalent series resistance), high voltage and large capacity and preparation method thereof |
| abstract | The invention discloses a laminated solid aluminum electrolytic capacitor with low ESR, high voltage and large capacity and a preparation method thereof, wherein the method comprises the following steps: s1: cutting the aluminum foil and then placing the cut aluminum foil in a stamping die for punching; s2: welding the aluminum foil punched in the S1 on Bar strips, and coating glue in the positive and negative isolation lines for drying; s3: electrifying the aluminum foil to form an aluminum foil; s4: impregnating and carbonizing the aluminum foil; s5: bonding and laminating the cathodes of the plurality of single capacitor chips to the lead frame through a laminating device; s6: the lead frame with the capacitor chip stacked in S5 is sent to a bonding apparatus; s7: coating edge sealing silver adhesive on one side of the negative laminated single capacitor chip; s8: packaging the laminated multilayer single chip by using epoxy resin, and curing to form a core package; s9: the core pack in S8 was subjected to aging molding. The invention fixes a plurality of groups of laminated chips on the lead frame, thereby improving the efficiency of subsequent processing, and the welding mode adopted by the invention not only has high efficiency, but also reduces the production cost. |
| priorityDate | 2021-12-13-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 25.