http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114115801-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ac31afbea1cbbb03498644721ffb4a62 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F7-523 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F7-523 |
| filingDate | 2021-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e8da50f6828d9504e2c36a34aca7fca4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_358c4275cf48fb934b148ee936df5490 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_dc067069aa53e2887e39cbf5f752c4c5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_21a09381fca2b56646c235f34d2e71f0 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_990a3a8b853157c57fccc0c4d9e39174 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_7c838d48003cb2b151a594ac65d70ef8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a8743c0ce099a3128f8fcf5e1f5e784d http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_97bcd96457035e5240bb6c7595fbf0b8 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f3a26808fd39c5af6db2d9af1f81ab06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_4c54452c353551182fe22c6a4a0916f3 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_df0864fc6f9a221110069bc49be85d98 |
| publicationDate | 2022-03-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-114115801-A |
| titleOfInvention | Storage-calculation integrated unit and method for realizing multiplication function |
| abstract | The invention discloses a storage-computation integrated unit for realizing multiplication function. The cell includes a collection transistor and a readout transistor formed on the same P-type silicon substrate; inputting a voltage to the readout transistor through the control gate to control and modulate the carriers as a first multiplier; a carrier collecting region of the collecting transistor collects carriers and stores the carriers to the charge coupling layer as a second multiplier; the charge coupling layer acts the current carrier on the silicon substrate of the readout transistor to form a multiplication relation; the carrier read region of the read transistor outputs carriers, which are applied by the first multiplier and the second multiplier, as an output result of the multiplication in the form of a current. The invention separates the collection and operation functions of the integrated storage-calculation device according to regions, effectively protects the reading function region when the device collects carriers, and can improve the service life, the durability and the reading precision of the integrated storage-calculation device. |
| priorityDate | 2021-11-23-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 33.