http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113937059-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_b5b43f4a86fc8f7ad28689d833acac53 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1042 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2221-1063 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5329 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76831 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-482 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5226 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B12-0335 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-7682 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 |
| filingDate | 2020-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3995c745acbb914791942d6cffc12288 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_5cdd2f7cee55fde63555561bbafe89cf http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bd82e11c7adb9033d1d3fa334cac3b07 |
| publicationDate | 2022-01-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113937059-A |
| titleOfInvention | Method for forming semiconductor structure and semiconductor structure |
| abstract | Embodiments of the present invention provide a method for forming a semiconductor structure and a semiconductor structure, and the method for forming a semiconductor structure includes: providing a substrate on which discrete bit line structures are formed; forming a first sacrificial layer on the sidewall of the bit line structure; forming A first dielectric layer that fills the gap between adjacent bit line structures; the first dielectric layer is patterned to form through holes, the through holes expose active regions in the substrate, and in the direction extending along the bit line structures, the through holes and The remaining first dielectric layers are alternately arranged; a second sacrificial layer is formed on the sidewall of the through hole, and the through hole is filled to form a contact plug; a contact structure is formed on the contact plug; the first sacrificial layer is removed to form a first air gap , removing the second sacrificial layer to form a second air gap. By forming the first air gap and the second air gap, the effect of reducing parasitic capacitance is good, and the formed air gap can be easily sealed. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114582796-A http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023184571-A1 |
| priorityDate | 2020-07-14-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 28.