| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_36333273e27f0db23ddddbf80ba79ba7
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_afdd9404179f36844cef7e4e120dc2f8 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-394
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-398
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-373
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G06F30-392 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G06F30-392 |
| filingDate |
2020-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e439d98404883471f992095140b1c4b9
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9bab42feed01e4a4e280ff7febfd732
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3def73993200162637f4b666495f1454
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9deb2184fcfe420020a35c6fea4c830e
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a213476b9e8e658747b744529a830c9c |
| publicationDate |
2022-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113919275-A |
| titleOfInvention |
Method for optimizing the layout of an integrated circuit |
| abstract |
The present disclosure relates to methods for optimizing the layout of integrated circuits. A method is provided in the present disclosure. The method includes several operations: generating a layout with a plurality of macros for the integrated circuit; adjusting the macros according to the channel area inserted between the pins; separating the channel widths of the channel areas for the macros; Dependencies between registers to adjust macros in the layout. |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116595938-B
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-116595938-A |
| priorityDate |
2020-09-21-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |