| abstract |
The invention discloses a neural network accelerator convolution computing device and method based on a systolic array. The structure of the device is composed of 64×64 isomorphic PE units to form a systolic array, including multiple weight input channels, data The input channel and the corresponding data (weight) gate the active signal. After the first activation of the systolic array starts, the enable signal becomes valid, and after all data calculations are completed, the enable signal is turned off. The weight data in the systolic array is transmitted from top to bottom, and the calculation result and weight valid signal of each PE unit are input to the next PE unit in the same column after passing through the first-level register to participate in the calculation. The feature map data and data valid signals in the systolic array are transmitted from left to right, and after passing through the first-level register, they are input to the next PE unit of a row to participate in the calculation. |