http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113852373-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_ca46be4e68fa1f5a8b2ef4ab654c490a |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-46 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H03M1-1009 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H03M1-46 |
| filingDate | 2021-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_3b88b846687b5c59f5319a06e33d7b3c http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_47cd432d58e8eedc7d875ed3d468cae9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_06b521d8bd35e2270ca89e042b8eb2b5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c9b35293d15b876a9778c1e5e0997bc1 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a9673b516db6baa643b7ad9105357f99 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2a1946b3ef29f007df4879ffd6581549 |
| publicationDate | 2021-12-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113852373-A |
| titleOfInvention | A pipelined domino successive approximation analog-to-digital converter |
| abstract | The invention provides a pipeline domino structure successive approximation type analog-to-digital converter, comprising: n+1 stage sub-ADC, multiple residual amplifiers and preset adjustment modules; the input end of the first stage sub-ADC is connected with the signal input end, It is used to obtain the input signal after sampling; the output end of the sub-ADC includes a first output end, and the first output end is connected with the preset adjustment module, and is used for inputting the 5-bit quantization code generated by each sub-ADC to the preset adjustment module, In order to make the preset adjustment module perform splicing and redundancy bit correction on the quantization code to obtain an analog-to-digital conversion result; the first to n stages of sub-ADCs also include a second output terminal, which is used for the residual signal generated by the sub-ADC to be processed by the residual difference. The signal amplified by the amplifier is used as the input signal and input to the next stage sub-ADC. The invention improves the conversion speed and precision of the SAR ADC, can correct the offset voltage in real time during the working process of the comparator, and prevent the performance of the sub-ADC from being affected by the offset accumulation. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-114499529-A |
| priorityDate | 2021-08-16-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 41.