http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113711353-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_03fc41c4e41cbd2c6eafe96ab0c9ce14 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2275 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2273 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-10 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B51-20 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-223 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2257 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11597 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11556 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-108 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-22 |
| filingDate | 2020-05-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2d6db4c4db3d2e09d61cefdb40fa599e |
| publicationDate | 2021-11-26-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113711353-A |
| titleOfInvention | Three-dimensional Ferroelectric Random Access Memory (FERAM) |
| abstract | Three-dimensional vertical memory string arrays include low-cost, low-power or high-density high-speed ferroelectric field effect transistor (FET) cells suitable for SCM applications. The memory circuit of the present invention provides random access capability. The memory strings may be formed over a planar surface of the substrate and include vertical gate electrodes extending longitudinally in a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrodes; (ii) a gate oxide (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in the oxide layer and isolated from each other by the oxide layer, wherein the gate electrode, the ferroelectric layer, the gate The electrode oxide layer, the channel layer, and each pair of adjacent semiconductor regions form a storage transistor of the memory string, and wherein a pair of adjacent semiconductor regions serve as source and drain regions of the storage transistor. |
| priorityDate | 2019-05-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 67.