http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113539948-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_5e829b93e1bdf87272f2aaf3baaaa0f4 http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c8fbf590463d3518a746d90a6a2c1c34 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-5283 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76898 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76879 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-76847 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-768 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-528 |
| filingDate | 2020-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c33a5161515fa37b4056885e3b3af1d5 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_9d1646e779e1d9950560efd8480f1fbd http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_45f90ee0546eafd0c18f7420e43c9307 |
| publicationDate | 2021-10-22-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113539948-A |
| titleOfInvention | Semiconductor structure and forming method thereof |
| abstract | A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate; forming a first interconnection line, a dielectric lamination covering the first interconnection line and a second dielectric layer covering the dielectric lamination on a substrate; forming a first interconnection trench located in the first region and a second interconnection trench located in the second region; forming a first hard mask layer for filling the first interconnection groove and a second hard mask layer for filling the second interconnection groove, wherein the etching resistance of the second hard mask layer is greater than that of the first hard mask layer; forming a first through hole penetrating through the first hard mask layer, the second dielectric layer and the dielectric laminated layer and a second through hole penetrating through the second hard mask layer and the second dielectric layer; and forming a super through hole interconnection structure positioned in the first through hole, a single-layer through hole interconnection structure positioned in the second through hole and a third interconnection line positioned in the first interconnection groove and the second interconnection groove. The invention is beneficial to improving the interconnection performance of the semiconductor structure. |
| priorityDate | 2020-04-20-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 22.