| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-02
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C17-16
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4078
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-1695
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-0483
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C8-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-22
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-24
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-2295
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-0251
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-409 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-409
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C11-4078 |
| filingDate |
2021-03-31-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_2b3dc93703ff689f022a66b98718523f
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_bf933d59b3a50b92d24259e6fbc32776 |
| publicationDate |
2021-10-19-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113517012-A |
| titleOfInvention |
Semiconductor device protection circuits and associated methods, devices, and systems |
| abstract |
Semiconductor device protection circuits and associated methods, apparatus, and systems are disclosed. A memory device may include a source SRC plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and the node. Additionally, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may be further configured to isolate the SRC plate from the ground voltage during an operating phase. |
| priorityDate |
2020-04-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |