| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_7a4ba732e996ccb96709867320c92feb |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78681
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-0673
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L27-088
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-823412
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/B82Y10-00
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-42392
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78696
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66795
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66439
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66787
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-785
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-775
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-1054
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78618
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66545
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-66522
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-02603
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L29-78684 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-78
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-336
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L29-10
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/B82Y10-00 |
| filingDate |
2021-04-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_f985a29b6890182d442e915f13ee5a01 |
| publicationDate |
2021-10-12-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113497151-A |
| titleOfInvention |
Semiconductor structure and method of forming the same |
| abstract |
The present invention discloses a semiconductor structure comprising: a first semiconductor stack and a second semiconductor stack, each of the first semiconductor stack and the second semiconductor stack comprising: a channel layer over the substrate and spaced apart from each other in a third direction, wherein the third direction is perpendicular to the first direction and the second direction; and a gate structure including: a gate dielectric layer formed around the corresponding channel layer; and forming On the gate dielectric layer is a gate electrode surrounding the channel layer, wherein the number of channel layers in the first semiconductor stack is different from the number of channel layers in the second semiconductor stack. The present invention selectively reduces the number of channel layers of a low-power device to reduce leakage current, thereby improving the electrical performance of the device. |
| priorityDate |
2020-04-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |