| abstract |
Microelectronic device interface configurations and related methods, devices, and systems are disclosed. The memory device may include a first row of power supply pads and a first row of input/input DQ pads. The memory device may further include a row of vias, wherein the first row of DQ pads is positioned at least partially between the row of vias and the first row of power supply pads. The memory device may also include a plurality of conductors, wherein each via of the row of vias is coupled to a power pad of the first row of power pads by an associated conductor of the plurality of conductors or the DQ pads in the first row of DQ pads. |