http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113421964-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02E10-549 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-011 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-021 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-041 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-801 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10N70-841 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-18 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L25-18 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L45-00 |
| filingDate | 2021-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2022-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2022-07-08-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113421964-B |
| titleOfInvention | 1S1R type memory integrated structure and preparation method thereof |
| abstract | The present invention provides a method for preparing a 1S1R type memory integrated structure, including preparing a gate and a resistive memory, and connecting the gate and the resistive memory in series. The preparation method uses two spin coating solutions with the same element composition and different concentrations and the anti-solvent to be used separately and deposited on two flexible conductive substrates through a low-temperature spin coating process, thereby realizing the two flexible conductive substrates. The resistive switching layer covered by the conductive surface has the same element composition and different thicknesses, and then the gate and the resistive switching memory can be obtained by depositing different metal materials on the surface of the resistive switching layer with different thicknesses to form different top electrodes through the step S3. The process is simple, and after applying forward voltage stimulation to the top electrode of the gate through the step S4, the gate and the resistive memory are connected in series to obtain the 1S1R type memory integrated structure, thereby realizing the 1S1R structure flexible integration. The invention also provides a 1S1R type memory integrated structure. |
| priorityDate | 2021-06-18-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 39.