http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113410152-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_f80f7502fa29eccce5d0ca3b654f4d96 |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/Y02D10-00 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B41-27 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L22-12 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H10B43-27 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11556 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-66 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L27-11582 |
| filingDate | 2021-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_ac824b574e526c2bdaf29b9a9a98d442 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_c8d7e2186c9846ac99d05069c3c010fa http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_a0b436094368dabd9016a4ed6d07a64a |
| publicationDate | 2021-09-17-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113410152-A |
| titleOfInvention | Void detection method for 3D NAND memory |
| abstract | The present application provides a method for detecting voids in a 3D NAND memory, including: removing a portion of a filling layer located on a plurality of stacked structures arranged at intervals; removing the second sacrificial layer and the adjacent second sacrificial layers of the filling layer. part between layers; removing the second insulating layer and the portion of the filling layer between adjacent second insulating layers; forming a protective layer covering the sidewalls and bottom of the substrate; using the first wet method The etch process processes the 3D NAND memory and performs void detection. In the void detection method provided by the present application, the filling layer is partially removed to expose the top surface of the part of the filling layer between the adjacent first sacrificial layers, and then a first wet etching process is used. The substrate is processed, and whether there is a void in the filling layer is determined by detecting whether there is an etching trace on the substrate, so as to prevent abnormal leakage of the 3D NAND memory. |
| isCitedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-115632044-B |
| priorityDate | 2021-06-02-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 32.