http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113380641-A
Outgoing Links
| Predicate | Object |
|---|---|
| assignee | http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_2a3e3b47a34c4443062b32c5fd645cda |
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13018 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-11462 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-13022 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-11 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-13 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L21-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-3128 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-56 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-31 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L21-60 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/H01L23-488 |
| filingDate | 2020-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor | http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_703827d35505cf5986e37a763d17f5e9 http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_85919092d6b035f15d7a73118ce13fad |
| publicationDate | 2021-09-10-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113380641-A |
| titleOfInvention | Manufacturing method of crystal grain packaging structure |
| abstract | The invention discloses a manufacturing method of a crystal grain packaging structure, which comprises the following operations. A conductive substrate having a plurality of grooves is provided. A die is disposed in each recess. Forming a conductive layer covering the die and the conductive substrate. Forming a patterned photoresist layer on the conductive layer, wherein the patterned photoresist layer has a plurality of openings exposing a plurality of regions of the conductive layer. A shield is formed over regions of the conductive layer. After the mask is formed, the patterned photoresist layer is removed. And selectively etching the conductive layer and the conductive substrate below the conductive layer to a predetermined depth by using the mask to form a plurality of conductive bumps and a plurality of electrodes, wherein the remaining conductive substrate comprises a bottom plate, the electrodes are positioned on the bottom plate, and the conductive bumps are positioned on the dies. And forming an upper sealing adhesive layer to cover the bottom plate and the crystal grains, wherein the shielding, the conductive bumps or the electrodes are exposed out of the upper sealing adhesive layer. The invention can achieve the miniaturization of the crystal grain packaging structure in the vertical direction and improve the heat dissipation effect of the power chip. |
| priorityDate | 2020-02-25-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
Total number of triples: 27.