| Predicate |
Object |
| assignee |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentassignee/MD5_c3a2f00e72ba6e4c09b6da573427fbed |
| classificationCPCAdditional |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-40615 |
| classificationCPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4072
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-20
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-106
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1039
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4093
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-1087
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C7-222
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4096
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C16-105
http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C11-4076 |
| classificationIPCInventive |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C16-10 |
| filingDate |
2021-02-01-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| inventor |
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_b8cfd28553c3fe3db8ce883f3e323c31
http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_e53d6146155d4dbcecfc88374e79f5b1 |
| publicationDate |
2021-08-27-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber |
CN-113314177-A |
| titleOfInvention |
Apparatus, system and method for latch reset logic |
| abstract |
The present invention relates to apparatus, systems and methods for latch reset logic. A bank may have local latches coupled between the local data bus and the bank. Some of the local latches may be shared local latches coupled to the first and second memory banks. The shared latch can latch data in response to the first clock signal and the second clock signal, and can be reset in response to a combined reset signal. A reset logic circuit may receive the clock signal and the first and second reset signals. The reset logic circuit may provide the combined reset signal based on the first and second clock signals and the reset signal. The clock signal may be a column valid command, and the reset signal may be the waveform of a row valid command used as part of an access operation on the first memory bank or the second memory bank (eg, falling along). |
| isCitedBy |
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113393873-A
http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113393873-B |
| priorityDate |
2020-02-07-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type |
http://data.epo.org/linked-data/def/patent/Publication |