| abstract |
An improved memory cell architecture comprising a nanostructured field effect transistor and a horizontal capacitor extending at least partially below the nanostructured field effect transistor. In one embodiment, a semiconductor device includes a channel structure over a semiconductor substrate, a gate structure surrounding the channel structure, a first source/drain region adjacent to the gate structure, and a A capacitor extending under the first source/drain region and the gate structure in a cross-sectional view. |