http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113257293-B
Outgoing Links
| Predicate | Object |
|---|---|
| classificationCPCAdditional | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06137 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06527 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06177 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06155 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06151 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06135 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-06157 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02379 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2224-02375 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2924-1434 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L23-50 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L2225-06562 |
| classificationCPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L25-0657 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-02 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/G11C5-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentcpc/H01L24-06 |
| classificationIPCInventive | http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-06 http://rdf.ncbi.nlm.nih.gov/pubchem/patentipc/G11C5-02 |
| filingDate | 2021-01-11-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| grantDate | 2023-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationDate | 2023-02-03-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| publicationNumber | CN-113257293-B |
| titleOfInvention | Semiconductor device including arrayed power pads and associated semiconductor device package and system |
| abstract | The present application relates to semiconductor devices including arrayed power pads and associated semiconductor device packages and systems. According to some embodiments, a semiconductor device may include a memory array region and a peripheral region. The memory array area can include a number of memory cells and a number of array pads configured to receive an input voltage. The peripheral area may include a number of peripheral pads for interfacing with the memory array area. In these or other embodiments, the peripheral region can be arranged adjacent to a first edge of the semiconductor device, and the number of array pads can be arranged adjacent to a second edge of the semiconductor device. The second edge may be perpendicular to the first edge. The memory array region may also include array distribution conductors configured to variously electrically connect the number of memory cells to the number of array pads. A semiconductor device package and system are also disclosed. |
| priorityDate | 2020-01-28-04:00^^<http://www.w3.org/2001/XMLSchema#date> |
| type | http://data.epo.org/linked-data/def/patent/Publication |
Incoming Links
| Predicate | Subject |
|---|---|
| isDiscussedBy | http://rdf.ncbi.nlm.nih.gov/pubchem/compound/CID7156993 http://rdf.ncbi.nlm.nih.gov/pubchem/substance/SID426135032 |
Total number of triples: 29.