http://rdf.ncbi.nlm.nih.gov/pubchem/patent/CN-113161356-A

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filingDate 2021-03-04-04:00^^<http://www.w3.org/2001/XMLSchema#date>
inventor http://rdf.ncbi.nlm.nih.gov/pubchem/patentinventor/MD5_92772db98672779198768e5cdfd55ed4
publicationDate 2021-07-23-04:00^^<http://www.w3.org/2001/XMLSchema#date>
publicationNumber CN-113161356-A
titleOfInvention Memory device, semiconductor structure and method of forming the same
abstract The present disclosure provides a memory device, a semiconductor structure and a method for forming the same, and relates to the technical field of semiconductors. The forming method includes: providing a substrate, the substrate comprising a capacitor array area and an open area surrounding the capacitor array area; depositing a conductive layer on the substrate, the conductive layer covering the capacitor array area and the open area, and located in the conductive layer of the open area away from The sidewall of the capacitor array area has a step structure; a support structure is formed on the step structure; a mask layer is formed on the conductive layer, and the mask layer at least covers the capacitor array area and exposes the support structure; Conductive layer and support structure covered by mask layer to eliminate step structure. The method for forming the semiconductor structure of the present disclosure can prevent short circuit of the interconnect structure, reduce the risk of device failure, and improve product yield.
isCitedBy http://rdf.ncbi.nlm.nih.gov/pubchem/patent/WO-2023060728-A1
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Total number of triples: 35.